Field of the Invention
The present technology relates to a liquid crystal display device.
Description of the Background Art
There are various needs in the market of liquid crystal display devices, such as high resolution, reduction in size of a peripheral region around a display region, or reduction in cost.
For example, if an attempt to increase resolution is made, the number of gate lines and the number of source lines are increased with this attempt. If reduction in cost is to be simultaneously implemented, it is necessary that the number of gate lines and the number of source lines output from one integrated circuit (IC) chip are increased to suppress an increase in the number of necessary components.
In addition, reduction in size of an IC chip is also demanded to suppress a unit price of the IC chip. The increase in the number of output lines per one IC chip and the reduction in size of the IC chip lead to decrease in spaces between output terminals of the IC chip.
In order to decrease the space between the output terminals and to simultaneously reduce size of the peripheral region, wiring width and wiring space of lead-out lines connecting the output terminals and the display region are also decreased.
The decrease in the wiring width and wiring space of the lead-out lines wired between a drive circuit mounted on the peripheral region and the display region entails deterioration in yield. Further, there are a limit for a wiring width and a limit for a wiring space in manufacture. Therefore, there are also limits upon decreasing a wiring width and wiring space.
As one of methods for solving the problem of the limits upon decreasing the wiring width and the wiring space, a method for implementing a multilayer structure of lead-out lines has been proposed (see, for example, Japanese Patent Application Laid-Open No. 2006-171387). With this method, lead-out lines are wired in a plurality of different layers, and the lead-out lines are wired as being overlapped with each other in a plan view. According to this, more lead-out lines than the case where the lead-out lines are wired with the limited width and limited space in manufacture in a single layer can be wired without increasing the peripheral region.
It is generally considered that the demand of decreasing the wiring width and wiring space of lead-out lines is higher for a source-line side than for a gate-line side. In the case where a drive circuit is incorporated in a liquid crystal panel to reduce the number of components, a gate drive circuit is more likely to be set as the circuit incorporated into the panel than a source drive circuit, because the gate drive circuit has a more simple structure than the source drive circuit.
However, when lead-out lines at the source-line side are formed to have a multilayer structure, an effect caused by parasitic capacitance formed between the lead-out lines overlapped with each other in a plan view becomes a problem. Specifically, capacitance coupling through an insulating layer occurs between the lead-out lines, and this causes rounding of a waveform of a source signal.